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INTEGRATED CIRCUITS
DATA SHEET
SAA4978H Picture Improved Combined Network (PICNIC)
Product specification Supersedes data of 1998 Oct 07 File under Integrated Circuits, IC02 1999 May 03
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
CONTENTS 1 2 3 4 5 6 7 7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 7.2.6 7.2.7 7.2.8 7.2.9 7.2.10 7.2.11 7.2.12 7.2.13 7.2.14 7.2.15 7.2.16 FEATURES GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING INFORMATION FUNCTIONAL DESCRIPTION Analog input blocks Gain elements for automatic gain control (9 dB range) Clamp circuit, clamping Y to digital level 32 and UV to 0 (2's complement) Analog anti-aliasing prefilter 9-bit analog-to-digital conversion Digital processing blocks Overflow detection Y delay Transient noise suppression Non-linear phase filter after ADC 4 MHz notch Digital clamp correction for UV 4 : 4 : 4 downsampled to 4 : 2 : 2 or 4 : 1 : 1 Bus A format: interface formatting, timed with enabling signal (see Table 1 and Fig.9) Bus B format (see Table 1 and Fig.9) Time base correction and sample rate conversion Noise reduction Histogram Subtitle detection Black bar detection Bus C format (see Table 1) Bus D reformatter: the various input formats are all converted to the internal 9 bits 4 : 2 : 2 (see Table 1) Peaking Non-linear phase filter before DAC DCTI Border blank Analog output blocks Triple 10-bit digital-to-analog conversion Analog anti-aliasing post-filter PLL SNERT PSP Microcontroller Board level testability Power-on reset 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17
SAA4978H
CONTROL REGISTER DESCRIPTION LIMITING VALUES THERMAL CHARACTERISTICS CHARACTERISTICS APPLICATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
7.2.17 7.2.18 7.2.19 7.2.20 7.3 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8
1999 May 03
2
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
1 FEATURES
SAA4978H
* Clamp * Analog AGC * Triple YUV 9-bit Analog-to-Digital Converter (ADC) * Triple bypassable analog anti-alias filter * 4 MHz notch filter * Non-linear phase filter after ADC * 4 : 1 : 1 or 4 : 2 : 2 digital processing * 4 : 1 : 1 or 4 : 2 : 2 selectable I/O interface * Asynchronous digital input * Time base correction * Histogram analysis * Histogram modification * Subtitle detection * Black bar detection * Line memory based noise reduction (spatial) * Noise level measurement * Clamp noise reduction * Dynamic peaking * Energy measurement * Multi Picture-In-Picture (multi PIP) decimation * Differential Pulse Code Modulation (DPCM) data decompression for colour 3 QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD fclk S/N 4 PARAMETER analog supply voltage digital supply voltage analog supply current digital supply current clock frequency signal-to-noise ratio default settings VDDA = 3.45 V VDDD = 3.6 V CONDITIONS MIN. 3.15 3.0 - - - 50 TYP. 3.3 3.3 145 210 16 - MAX. 3.45 3.6 180 270 - - UNIT V V mA mA MHz dB 2 GENERAL DESCRIPTION The SAA4978H is a monolithic integrated circuit suitable either for 1fH or 2fH applications that contain a large variety of picture improvement functions. It combines analog-to-digital and digital-to-analog conversion for YUV signals, digital processing, line-locked clock regeneration and an 80C51 microcontroller core in one IC. * 2D-peaking and coring * Non-linear phase filter before DAC * Coaxial Transceiver Interface (CTI) * Triple 10-bit Digital-to-Analog Converter (DAC) * Triple bypassable analog reconstruction filter * Embedded microcontroller (80C51 core) * Programmable signal positioner * SNERT interface * I2C-bus user control interface * Boundary Scan Test (BST).
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME QFP160 DESCRIPTION plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height VERSION SOT322-2
SAA4978H
1999 May 03
3
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1999 May 03
VDDD1 to VDDD4 VSSD1 to VSSD4 BGEXT 17 64, 87, 100, 135 DIFFIN 21 64, 90, 134, 139 BAND GAP REFERENCES Ref L Ref H various bias controls YIN 23 Y DELAY MAJORITY FOLLOWER FILTER CLAMP 25 UV CLAMP CORRECTION TRIPLE AGC 9-BIT TRIPLE ANALOG PREFILTER ADC TRIPLE 9-BIT UIN VIN 26 CLP OVERFLOW DETECTOR
5
Philips Semiconductors
Picture Improved Combined Network (PICNIC)
BLOCK DIAGRAM
WEA
YA0 to YA8
UVA0 to UVA8
UVB0 to UVB8
YB0 to YB8
WEB CLKAS
62
53 to 61 3-STATE
43 to 51 84 to 76 75 to 67 66 85
SYNCHRONIZE DITHER NON-LINEAR PHASE FILTER 4 MHz NOTCH MUX A
5 DITHER MUX REFORMATTER 5 FORMATTER DOWNSAMPLER 11 10 DOWNSAMPLER DITHER UPSAMPLER MUX
TIME BASE CORRECTION/ SAMPLE RATE CONVERTER
B
VDDA1 to VDDA4 VSSA1 to VSSA4
11, 22, 24, 31
bus A
bus B
SKEWEN
SKEW
4
SAA4978H
13, 16, 27, 32 CLP
RED
WEA
BLANKING BORDER PIXREP HREF
HA C D
WEC
IEC
BST/TEST
PSP
E F G 36 37 38 39 40 41 18 19 29 30 158 157 10
MHB172
TEST TRST TMS
TDI
TDO TCK
HDFL VDFL
VA
HREFEXT
INT1
INT0
FBL
Product specification
SAA4978H
Standard bus width in data path is 9 bits; exceptions are marked.
Fig.1 Block diagram (continued in Fig.2).
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1999 May 03
SPECTRAL MEASUREMENT NOISE ESTIMATION A SUBTITLE DETECTION BLACK BAR DETECTION NOISE REDUCTION HISTOGRAM MODIFICATION B
Philips Semiconductors
Picture Improved Combined Network (PICNIC)
YC8 to WEC IEC YC0
UVC8 to UVC0
UVD0 to UVD8
YD0 to YD8
RED
113
112
114 to 122 3-STATE
124 to 132
91 to 99
101 to 109
110
UNDITHER DITHER MUX DOWNSAMPLER DITHER 5 FORMATTER MUX
SPECTRAL MEASUREMENT DYNAMIC 10 PEAKING NON-LINEAR 10 PHASE FILTER
12
YOUT
5 REFORMATTER UPSAMPLER 10 MUX DPCM DECODER DCTI 10 BORDER BLANK DAC TRIPLE 10-BIT TRIPLE ANALOG POST-FILTER 14 UOUT
DITHER 8 DPCM CODER bus C 4
4
15
VOUT
bus D PIXREP BLANKING
5
SPECIAL FUNCTION REGISTERS VARIOUS REGISTERS AUXILIARY RAM PROGRAM ROM
BORDER
SAA4978H
SKEWEN CL16 CL16 CL16 HREF SKEW CL16 CL32
C D DATA8 P1.1 INT1 INT0 P1.4 E F G 1 2 140 149 to to 147 156 136 137 138 160 159 8 OR 9 5 4 6 7 42, 63, 86, 111, 133, 3 52, 123, 148 88 80C51 MICROCONTROLLER CORE bone P1.5 WATCHDOG FREQUENCY GUARD
PLL
EA PSEN
P3.5 P3.4 P1.2 P1.3 P1.7 P1.6 RST
CRYSTAL OSCILLATOR 89 28 34 35
MHB173
SNDA SNCL
P2.7 P0.7 EA ALE to to T1 PSEN P2.0 P0.0
T0
RSTR SCL RST RSTW SDA
WDRST
VSSO1 to VSSO6
VDDO1 to VDDO3
CLK16 CLK32 HA
OSCI
OSCO
Product specification
SAA4978H
Standard bus width in data path is 9 bits; exceptions are marked.
Fig.2 Block diagram (continued from Fig.1).
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
6 PINNING INFORMATION SYMBOL SNDA SNCL VSSO6 SCL SDA RST WDRST RSTW RSTR FBL VDDA1 YOUT VSSA1 UOUT VOUT VSSA2 BGEXT HDFL VDFL AGND DIFFIN VDDA2 YIN VDDA3 UIN VIN VSSA3 HA VA HREFEXT VDDA4 VSSA4 VSSX OSCI OSCO TEST TRST TMS TDI TDO 1999 May 03 PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SNERT data input/output SNERT clock output DESCRIPTION
SAA4978H
digital microcontroller I/O ground 6; internally connected to all other VSSO pins I2C-bus serial clock input (P1.6) I2C-bus serial data input/output (P1.7) microcontroller reset input watchdog reset output reset write signal output/SNERT reset (only PALplus) Port 1.2 reset read signal output/SNERT reset (SAA4991WP or SAA4992H) Port 1.3 fast blanking input to PSP and Port 1.4 analog back-end supply voltage 1 Y analog output analog back-end ground 1 U analog output V analog output analog input ground 2; internally connected to substrate band gap external/reference currents input horizontal synchronization signal output, deflection part vertical synchronization signal output, deflection part analog ground differential Y input analog input supply voltage 2 Y analog input analog input supply voltage 3 U analog input V analog input analog input ground 3; internally connected to substrate horizontal synchronization input, acquisition part vertical synchronization input, acquisition part horizontal reference external output analog PLL supply voltage 4 analog PLL ground 4; internally connected to substrate oscillator ground oscillator input oscillator output test input/external 32 MHz clock input BST reset input BST test mode select input BST test data input BST test data output 6
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SYMBOL TCK VSSO1 UVA0 UVA1 UVA2 UVA3 UVA4 UVA5 UVA6 UVA7 UVA8 VDDO1 YA0 YA1 YA2 YA3 YA4 YA5 YA6 YA7 YA8 WEA VSSO2 VDDD1 VSSD1 WEB YB8 YB7 YB6 YB5 YB4 YB3 YB2 YB1 YB0 UVB8 UVB7 UVB6 UVB5 UVB4 UVB3 1999 May 03 PIN 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 BST test clock input digital bus A/B ground 1; internally connected to all other VSSO pins bus A output UVL bus A output UV0 bus A output UV1 bus A output UV2 bus A output UV3 bus A output UV4 bus A output UV5 bus A output UV6 bus A output UV7 DESCRIPTION
SAA4978H
digital I/O bus A/B supply voltage 1; internally connected to all other VDDO pins bus A output YL bus A output Y0 bus A output Y1 bus A output Y2 bus A output Y3 bus A output Y4 bus A output Y5 bus A output Y6 bus A output Y7 write enable bus A output digital bus A/B ground 2; internally connected to all other VSSO pins digital core supply voltage 1; internally connected to all other VDDD pins digital core ground 1; internally connected to all other VSSD pins write enable bus B input bus B input Y7 bus B input Y6 bus B input Y5 bus B input Y4 bus B input Y3 bus B input Y2 bus B input Y1 bus B input Y0 bus B input YL bus B input UV7 bus B input UV6 bus B input UV5 bus B input UV4 bus B input UV3 bus B input UV2 7
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SYMBOL UVB2 UVB1 UVB0 CLKAS VSSO3 VDDD2 CLK16 CLK32 VSSD2 UVD0 UVD1 UVD2 UVD3 UVD4 UVD5 UVD6 UVD7 UVD8 VDDD3 YD0 YD1 YD2 YD3 YD4 YD5 YD6 YD7 YD8 RED VSSO4 IEC WEC YC8 YC7 YC6 YC5 YC4 YC3 YC2 YC1 YC0 1999 May 03 PIN 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 bus B input UV1 bus B input UV0 bus B input UVL asynchronous clock input DESCRIPTION
SAA4978H
digital I/O bus B/clock ground 3; internally connected to all other VSSO pins digital core supply voltage 2; internally connected to all other VDDD pins 16 MHz clock output 32 MHz clock output digital core ground 2; internally connected to all other VSSD pins bus D input UVL bus D input UV0 bus D input UV1 bus D input UV2 bus D input UV3 bus D input UV4 bus D input UV5 bus D input UV6 bus D input UV7 digital core supply voltage 3; internally connected to all other VDDD pins bus D input YL bus D input Y0 bus D input Y1 bus D input Y2 bus D input Y3 bus D input Y4 bus D input Y5 bus D input Y6 bus D input Y7 read enable bus D output digital I/O bus C/D ground 4; internally connected to all other VSSO pins input enable bus C output write enable bus C output bus C output Y7 bus C output Y6 bus C output Y5 bus C output Y4 bus C output Y3 bus C output Y2 bus C output Y1 bus C output Y0 bus C output YL 8
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SYMBOL VDDO2 UVC8 UVC7 UVC6 UVC5 UVC4 UVC3 UVC2 UVC1 UVC0 VSSO5 VSSD3 VDDD4 EA PSEN ALE VSSD4 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 VDDO3 P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 INT0 INT1 T0 T1 PIN 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 bus C output UV7 bus C output UV6 bus C output UV5 bus C output UV4 bus C output UV3 bus C output UV2 bus C output UV1 bus C output UV0 bus C output UVL DESCRIPTION
SAA4978H
digital I/O supply voltage 2 to bus C/D; internally connected to all other VDDO pins
digital I/O ground 5 to bus D and microcontroller; internally connected to all other VSSO pins digital core ground 3; internally connected to all other VSSD pins digital core supply voltage 4; internally connected to all other VDDD pins external access output (active LOW) program store enable output (active LOW) address latch enable output digital core ground 4; internally connected to all other VSSD pins Port 2 data input/output signal 7 Port 2 data input/output signal 6 Port 2 data input/output signal 5 Port 2 data input/output signal 4 Port 2 data input/output signal 3 Port 2 data input/output signal 2 Port 2 data input/output signal 1 Port 2 data input/output signal 0 microcontroller I/O pad supply voltage 3 Port 0 data input/output signal 7 Port 0 data input/output signal 6 Port 0 data input/output signal 5 Port 0 data input/output signal 4 Port 0 data input/output signal 3 Port 0 data input/output signal 2 Port 0 data input/output signal 1 Port 0 data input/output signal 0 interrupt 0, I/O Port 3.2 (active LOW) interrupt 1, I/O Port 3.3 (active LOW) timer 0 I/O Port 3.4 timer 1 I/O Port 3.5
1999 May 03
9
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SAA4978H
160
handbook, halfpage
121
1
120
SAA4978H
40
81
41
80
MHB174
Fig.3 Pin configuration.
7
FUNCTIONAL DESCRIPTION
The SAA4978H consists of the following main functional blocks: * Analog preprocessing and analog-to-digital conversion * Digital processing at 1fH level * Digital processing at 2fH level * Digital-to-analog conversion * Line-locked clock generation * Crystal oscillator * Control interfacing I2C-bus and SNERT * Register I/O * Programmable Signal Positioner (PSP) * 80C51 microcontroller core * Board level testability provisions. 7.1 7.1.1 Analog input blocks GAIN ELEMENTS FOR AUTOMATIC GAIN CONTROL (9 dB RANGE)
According to this specification, a lift of 6 dB up to a drop of 3 dB may be necessary with respect to the nominal values. The gain setting within the required minimum 9 dB range is performed digitally via the internal microcontroller. For this purpose a gain setting digital-to-analog converter is incorporated. The smallest step in the gain setting should be hardly visible on the picture, this can be met with smaller steps of 0.4%/step. Luminance and chrominance gain settings can be separately controlled. The reason for this split is that U and V may have already been gain adjusted by an Automatic Chrominance Control (ACC), whereas luminance is to be adjusted by the SAA4978H AGC. However, for RGB originated sources, Y, U and V should be adjusted with the same AGC gain. 7.1.2 CLAMP CIRCUIT, CLAMPING Y TO DIGITAL LEVEL 32 AND UV TO 0 (TWOS COMPLEMENT)
A variable amplifier is used to map the possible YUV input range to the analog-to-digital converter range e.g. as defined for SCART signals. 1999 May 03 10
A clamp circuit is applied to each input channel, to map the colourless black level in each video line (on the sync back porch) to level 32 at 9 bits for Y and to the centre level of the converters for U and V. During the clamp period, an internally generated clamp pulse is used to switch-on the clamp action.
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
A voltage controlled current source construction, which references to voltage reference points in the ladders of the analog-to-digital converters, provides a current on the input of the YUV signals in order to bring the signals to the correct DC value. This current is proportional to the DC error, but is limited to 150 A. It is essential that the clamp current becomes zero with a zero error and that the asymmetry between positive and negative clamp currents is limited to within 10%. When the clamping action is off, the residual clamp current should be very low, so that the clamp level will not drift away within a video line. The clamp level in the Y channel has a minimum value of 600 mV to ensure undisturbed clamping for maximum Y input signals with top sync levels up to 600 mV. In order to improve common mode rejection it is recommended to connect the same source impedance as used in the YIN input at the DIFFIN input to ground. 7.1.3 ANALOG ANTI-ALIASING PREFILTER 7.2.2 Y DELAY
SAA4978H
The Y samples can be shifted onto 4 positions with respect to the UV samples. This shift is meant to account for a possible difference in delay prior to the SAA4978H, e.g. from a prefilter in front of an analog-to-digital converter. The zero delay setting is suitable for the nominal case of aligned input data according to the interface format standard. One setting provides one sampleless delay in Y, the other two settings provide more delay in the Y path. 7.2.3 TRANSIENT NOISE SUPPRESSION
A 3rd-order linear phase filter is applied to each of the Y, U and V channels. It provides a notch on fclk (16 MHz at Y, U and V) to strongly prevent aliasing to low frequencies, which would be the most disturbing. The bandwidth of the filters is designed for -3 dB at 5.6 MHz. The filters can be bypassed if external filtering with other characteristics is desired. In the bypass mode the gain accuracy of the front-end part is 4% instead of 8% for the filter-on mode. 7.1.4 9-BIT ANALOG-TO-DIGITAL CONVERSION
A circuit is added in the luminance channel to suppress the typical multi-step trip level noise. This majority follower filter compares the neighbouring pixels to a +1 or -1 LSB difference. If the majority of these differences is +1 then 1 is added to the actual pixel. If the majority of these differences is -1 then 1 is subtracted from the actual pixel. The number of pixels included in the filter is selectable; 1 (bypass), 3, 5, 7 or 9. 7.2.4 NON-LINEAR PHASE FILTER AFTER ADC
The non-linear phase filter adjusts for possible group delay differences in the luminance channel. The filter coefficients are [-L x (1 - u); 1 + L; -L x u]; where L determines the strength of the filter and u determines the asymmetry. The effect of the asymmetry is that for higher frequencies the delay is decreased for u 0.5. Settings are provided for L = 0, 116, 216 and 316 and u = 0, 14 and 12. 7.2.5 4 MHZ NOTCH
Three identical multi-step type analog-to-digital converters are used to convert the Y, U and V inputs with a 16 MHz data rate. The ADCs have a 2-bit overflow detection, and an underflow detection for U and V, to be used for AGC control. The 2 bits are coded for one in-range level and three overflow levels; 1 dB, 1 to 2 dB and 2 to 3 dB. 7.2 7.2.1 Digital processing blocks OVERFLOW DETECTION
The 4 MHz notch provides a zero on 14 of the sample frequency. With fs = 16 MHz the notch is thus at 4 MHz. The 3 dB notch width is 2 MHz. The filter coefficients are 1 x [-1; 0; 5; 0; 5; 0; -1]. This filter gives a relative gain of 8 0.75 dB at 1.7 and 6.3 MHz. The notch can be bypassed without changing the group delay. 7.2.6 DIGITAL CLAMP CORRECTION FOR UV
A histogram of the three overflow levels is made every field and can be read in a 2-byte accuracy. An input selector defines which ADC is monitored. In the event of U or V selection the underflow information is also added to the first histogram level, in this way the data can be handled as out-of-range information. The histogram content provides information for the AGC to make an accurate estimate of the decrease in gain, in the event of overflow for luminance or out-of-range detection for U and V.
During 32 samples within the active clamping the clamp error is measured and accumulated to determine a low-pass filtered value of the clamp error. A vertical recursive filter is then used to further reduce this error value. This value can be read by the microcontroller or be used directly to correct the clamp error. It is also possible for the microcontroller to give a fixed correction value.
1999 May 03
11
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
7.2.7 4 : 4 : 4 DOWNSAMPLED TO 4 : 2 : 2 OR 4 : 1 : 1
SAA4978H
It is possible, in bus B reformatter, to invert the UV data so that the SAA4978H can handle any polarity convention of the UV data. In the event of an asynchronous input the clock has to be provided externally to pin CLKAS. When applying an external PALplus decoder with 30 ms processing delay, the vertical field start can be set via software in a PSP register. For "CCIR 656" standard data format input, inversion of the MSB of the (synchronized) bus B UV input can be selected. Synchronization signals included in this format will be ignored. 7.2.10 TIME BASE CORRECTION AND SAMPLE RATE
CONVERSION
4 : 4 : 4 data is downsampled to 4 : 2 : 2, by first filtering with a [1; 0; -7; 0; 38; 64; 38; 0; -7; 0; 1] filter, before being subsampled by a factor of 2. The U and V samples from the 4 : 2 : 2 data are filtered again by a [-1; 0; 9; 16; 9; 0; -1] filter, before being subsampled a second time by a factor of 2. Bypassing this function keeps the data in the 4 : 2 : 2 format. 7.2.8 BUS A FORMAT: INTERFACE FORMATTING, TIMED WITH ENABLING SIGNAL (see Table 1 and Fig.9)
The chosen 4 : 1 : 1 or 4 : 2 : 2 formatted output data is presented to bus A (YUV_A bus), consistent with the WEA data enable signal. After the rising edge of WEA the first, respectively second, data word contains the first phase of the 4 : 1 : 1 or 4 : 2 : 2 format, depending on the qualifier respectively prequalifier mode of WEA. If the data has to be formatted to 8 bits, a choice can be made between rounding and dithered rounding. Dithered rounding may be applied in the sense that every odd output sample has had an addition of 0.25 LSB (relative to 8 bits) before truncation and every even output sample has had an addition of 0.75 LSB before truncation. In this way, on average, correct rounding is realized (no DC shift). Especially for low frequency signals, the resolution is increased by a factor of 2 by the high frequency modulation. The phase of dithering can be switched 180 from line-to-line, field-to-field or frame-to-frame, in order to decrease the visibility of the dithering pattern. The not connected output pins of bus A, including WEA (depending on the application), can be set to 3-state to allow short-circuiting of these pins at board production. Short-circuiting at not connected outputs can not be tested by Boundary Scan Test (BST). For outputs in 3-state mode it is not allowed to apply voltages higher than VDDO + 0.3 V. 7.2.9 BUS B FORMAT (see Table 1 and Fig.9)
The Time Base Correction (TBC) and Sample Rate Conversion (SRC) block provides a dynamically controlled delay with an accuracy of up to 164 of a pixel and a range of -0.5 to +0.5 lines (plus processing delay). The time base correction block has an input for skew data. This skew data can be the phase error measured by a HPLL, which is located in the PLL block of the SAA4978H. The skew is used as a shift of the complete active video part of a line. Added with a static (user controlled) shift, up to 12 video line (32 s) can be shifted in both directions, related to a nominal 12 line delay. For sample rate conversion, the delay is also varied along the line with the subpixel accuracy. With a zero-order variation of the delay, a linear compress or expand function can be obtained. The range for the compression factor is 0 to 2, meaning infinite zoom up to a compression with a factor of 2. With a 2nd-order variation of the delay added to the control, the compression factor can be modulated with a parabolic shape, thus giving a panoramic view option to display e.g. 4 : 3 video on a 16 : 9 screen or vice versa. The static shift may also be used to make the delay of the SAA4978H plus periphery equal to an integer number of lines. This is useful for 1fH applications, in which the horizontal sync signal is not delayed with the video data. This will then make the function of time base correction obsolete for 1fH applications. Another main task for the sample rate converter is to resynchronize external data at a non-system clock sample rate, for instance, MPEG decoder signals at 13.5 MHz. A requirement for these signals is that they are line and frame locked to the SAA4978H.
Bus B can accommodate the following formats; 4 : 1 : 1 serial, 4 : 2 : 2 parallel, 4 : 2 : 2 double clock UYVY, all synchronous and asynchronous. All external formats are selectable with prequalifier or qualifier WEB. All of the various input formats are converted to the internal 9 bits 4 : 2 : 2. For the 8-bit inputs, the LSB of the input bus should be connected externally to a fixed logic level. In the event of a 4 : 1 : 1 input, the U and V channels are reformatted and upsampled by generating the extra samples with a 116 x [-1; 9; 9; -1] filter. The other U and V samples remain equal to the original 4 : 1 : 1 sample values.
1999 May 03
12
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
7.2.11 NOISE REDUCTION
SAA4978H
The histogram acquisition uses 32 baskets on the grey scale from (ultra) black to (ultra) white. Pixels that are found around the centre of a basket increase a counter for that basket with the value 8, pixels that come around the edge between two baskets increase the counters in both baskets, such as 3 in the left one and 5 in the right one. By this method, the quantization distortion is overcome from having a discrete set of baskets. Between acquisition of the histogram and correction of the transfer curves, the microcontroller included in the SAA4978H processes the counter values from the 32 baskets. The outcome of the microcontrollers algorithm defines a differential transfer curve for the luminance. This means that only differences from a 1 : 1 transfer curve are coded. This is done in 32 LUT points, with a linear interpolation for all input values in between the LUT points. When changes are made to the luminance level of pixels, the saturation has to be restored by using the same relative gain for the U and V channels. The histogram data also provides the information of the minimum and maximum levels of Y, U and V, by which the microcontroller can affect an AGC gain before the video analog-to-digital conversion. Another main part of the histogram is the display-bars block. This block can insert up to 32 horizontal bars in the YUV data path. Size, spacing, luminance, colour and length are fully programmable. This can be used to construct a visual display of the histogram or transfer curve. 7.2.13 SUBTITLE DETECTION
The noise reduction part consists of clamp noise reduction and spatial noise reduction for low frequency noise. Within this ensemble a two dimensional band split is used, enabling also the functions of 2D low passing, adding the multi Picture-In-Picture (multi PIP) function and 2D peaking. The clamp noise reduction is realized with an adaptive temporal recursive filter. This filter will correct the DC level of each line when it is varying from field-to-field in the segments with the least likely movement. This clamp noise filtering is intended to correct for clamp errors in a complete chain, which cannot be removed with traditional clamping on the back porch of the video. Clamp noise is only reduced for luminance. The spatial noise reduction is targeted for reduction of the mid frequency noise spectrum, where adaptive filtering combines pixels around the centre pixel and pixels from the lines above in a recursive way. This spatial noise reduction is only realized for luminance. The 2D low-pass filter is a [1; 2; 1] filter in both the horizontal and vertical direction. 2D high-pass is realized by taking the centre tap and subtracting the 2D low-pass output from it. Also added in the 2D high-pass is the vertical low-passed data, which is subtracted from the centre tap and multiplied by a user selectable gain (0 to 78). The 2D high-pass data is multiplied by a user selectable gain of 0 and 24 to 84 and cored before adding it to the 2D low-pass branch for the 2D peaking function. The HF signal bypasses both the LF temporal and the spatial noise reduction, therefore sharpness in the high frequencies is not reduced by the noise reduction parts. The factor 0 on the HF signal yields a pure 2D low-passed signal at the output. Multi PIP with pure subsampling of this signal yields a much better result than without the low-pass operation. 7.2.12 HISTOGRAM
Histogram modification consists of acquiring the histogram of the luminance levels and correcting the luminance transfer curve in order to provide more perceptual contrast in the picture. For economy, a subsampling is realized on the video with a factor of 4 before the histogram is produced. From line-to-line, a two pixel offset is used on the subsample pattern.
Subtitle detection searches in a large area of the video field for patterns that are characteristic for subtitles. The expectation is to encounter in a video line a considerable number of crossings through both a dark grey and a light grey threshold and in its vicinity also crossings in the other direction. This part is realized with valid crossing (event) counting on each line in the target area. This event value is stored for 128 lines in the subtitle RAM, which is located at the top of the auxiliary RAM. The subtitle logic has higher priority to access the subtitle RAM than the microcontroller. The internal microcontroller can filter out this data. In a number of adjacent lines, there must be a similar high count value for the number of events. If this condition holds then the detection of subtitles on that vertical position is more definite.
1999 May 03
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Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
This information can be used in combination with other information on how to display the video source on the screen. Such decisions are made entirely by the internal microcontroller. 7.2.14 BLACK BAR DETECTION 7.2.16
SAA4978H
BUS D REFORMATTER: THE VARIOUS INPUT
FORMATS ARE ALL CONVERTED TO THE INTERNAL
9 BITS 4 : 2 : 2 (see Table 1) Bus D can handle 4 : 1 : 1 external 8 or 9 bits, 4 : 2 : 2 external 8 or 9 bits, 4 : 2 : 2 internal 9 bits and DPCM 4 : 2 : 2. Bus D is selectable in 1fH and 2fH mode. In 1fH mode the internal input can also be used. For dithered 8-bit luminance signals an undither block is provided that restores the 9th bit for low frequency and low noise. This is needed before the peaking circuit to prevent amplification of the 12fs dither modulation. In the event of 8-bit inputs, the LSB of the input bus should be externally connected to a fixed logic level. In the event of a 4 : 1 : 1 input, the U and V channels are reformatted and upsampled by generating the extra samples with a 116 x [-1; 9; 9; -1] filter. The other U and V samples remain equal to the original 4 : 1 : 1 sample values. 7.2.17 PEAKING
Black bar detection searches in the upper and in the lower part of the screen to respectively the last black line and the first black line. To avoid disturbances of Logos in the video, measurements can be performed in only the horizontal centre part of the lines. 7.2.15 BUS C FORMAT (see Table 1)
The U and V samples from the 4 : 2 : 2 data are filtered again by a [-1; 0; 9; 16; 9; 0; -1] filter, before being subsampled by a factor of 2. Bypassing this function keeps the data in the 4 : 2 : 2 format. Should it be required to format the data to 8 bits, a choice can be made between rounding and dithered rounding. Dithered rounding may be applied in the sense that every odd output sample has had an addition of 0.25 LSB (relative to 8 bits) before truncation and every even output sample has had an addition of 0.75 LSB before truncation. In this way, normally, correct rounding is realized (no DC shift). Especially for low frequency signals, the resolution is increased by a factor of 2 by the high frequency modulation. The phase of dithering is switched 180 from line-to-line, field-to-field or frame-to-frame in order to decrease the visibility of the dithering pattern. This block also performs the subsampling for multi PIP, with subsampling factors of 1, 2, 3 and 4. Another output format at bus C is Differential Pulse Code Modulation (DPCM) 4 : 2 : 2. This data compression method is applied on the U and V channels, and gives a 50% data reduction. In this way it is possible to convert a 4 : 2 : 2 picture to 2fH using a single 12-bit wide field memory. This format is especially useful for graphics conversion with high amplitude and high saturation input signals. The not connected output pins of bus C including WEC and IEC (depending on the application) can be set to 3-state to allow short-circuiting of these pins at board production. Short-circuiting at not connected outputs can not be tested by BST. For outputs in 3-state mode it is not allowed to apply voltages higher than VDDO + 0.3 V.
Peaking in the SAA4978H can be used in two ways: 1. The first way is to give the luminance a linear boost of the higher frequency ranges, which makes no distinction between small and large details or edges. 2. The second way is to use the peaking dynamically, in order to boost smaller details and provide less gain on large details and edges. The effect is detail enhancement without the creation of unnaturally large overshoots and undershoots on large details and edges. Basically, the three peaking filters (1 high-pass and 2 band-pass) filter the incoming luminance signal. The high-pass filter is made with [-1; 2; -1] coefficients, giving a maximum throughput at 12fs (equals 8 MHz). The first band-pass filter has [-1; 0; 2; 0; -1] coefficients, giving a maximum throughput at 14fs (equals 4 MHz). The second band-pass filter has a cascade of [-1; 0; 0; 2; 0; 0; -1] and [1; 2; 1] coefficients, giving a maximum throughput at 2.38 MHz. With a separate gain control on each of the peaking filters [possible gain settings of (0, 116, 216, 316, 416, 516, 616 and 816)], a desired frequency characteristic can be obtained with steps of maximum 2 dB gain difference at the centre frequencies.
1999 May 03
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Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
The sum of the filter outputs is fed through a coring circuit with a user definable transfer curve between -7 and +7 LSB at a 12-bit level. The definition of the coring LUT is realized with two control registers. Herein, for each of the points in the transfer curve, the user can define an output between 0 and the input value. For the LUT points +7 (and -7), a choice can be made from (-4) +4 to (-7) +7. By setting control bit CORING to LOW, the coring transfer curve is switched to a coarse coring which is only dependent on the threshold (see Fig.13). The so formed peaking signal can be added to the original luminance signal, the sum of which then becomes the 9-bit output signal (black-to-white), with an additional DA shift fitting within 10 bits. For dynamic use of the peaking circuit, an additional gain is provided on the peaking signal. This gain is made dependent on the energy in the peaking signal. To overcome an unwanted coring on structured small signals, the output of the low-pass filter is also used to monitor if the high frequency contents are large enough to refrain from coring. Therefore the coring is set off if the HF energy level rises above a user definable threshold. Spectral measurements are performed with the spectr_meas subpart, by calculating the sum of the absolute values from a chosen one of the three (high-pass and band-pass) filter outputs over a vertical window in a video field. With this window it is possible to disable subtitles. The maximum value of the chosen filter output within a windowed video field is also monitored. For the generally lower HF contents of the video signal, a weighting by a factor 4 can be switched in, while measuring on the High-Pass Filter (HPF). 7.2.18 NON-LINEAR PHASE FILTER BEFORE DAC 7.2.19 DCTI
SAA4978H
The Digital Colour Transient Improvement (DCTI) is intended for U and V signals originating from a 4 : 1 : 1 source. Horizontal transients are detected and enhanced without overshoots by differentiating, making absolute and again differentiating the U and V signals separately. This signal is used as a pointer to make a time modulation. This results in a 4 : 4 : 4 U and V bandwidth. To prevent third harmonic distortion, typical for this processing, a so called `over the hill protection' prevents peak signals from becoming distorted. It is possible to control gain, width, connect U and V and over the hill range via the microcontroller. At the output of the DCTI a post-filter is situated to make a correction for the simple upsampling in DCTI which is a linear interpolation [1; 2; 1]. The post-filter coefficients are [-1; 2; 6; 2; -1], convolution of both filters gives [-1; 0; 9; 16; 9; 0; -1]. This post-filter should only be used when the DCTI is off, and the source material is 4 : 2 : 2 bandwidth. 7.2.20 BORDER BLANK
The border and blanking processing is operating at a 4 : 4 : 4 level, just before the analog-to-digital conversion. Here it is possible to generate a blanking window and within this window a border window. The blanking window is used to blank the non-visible part of the output to the clamp level. The border window is the visible part of the video that contains no video, such as the sides in compression mode, this part can be programmed to display any luminance or colour level in an 8-bit accuracy; pixel repetition is also possible here. In case of multi PIP this block can generate separation borders in the horizontal and vertical direction.
This non-linear phase filter adjusts for possible group delay differences in the Y, U and V output channels, and for sinus x/x bandwidth loss of the ADCs. The filter coefficients are [-L x (1 - u); 1 + L; -L x u]; where L determines the strength of the filter and u determines the asymmetry. The effect of the asymmetry is that for higher frequencies the delay is decreased for u 0.5. Settings are provided for L = 0, 18, 28, 38 and u = 0, 14, 12.
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Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
7.3 7.3.1 Analog output blocks TRIPLE 10-BIT DIGITAL-TO-ANALOG CONVERSION 7.3.6 MICROCONTROLLER
SAA4978H
Three identical DACs are used to convert Y, U and V with a 32 or 16 MHz data rate. 7.3.2 ANALOG ANTI-ALIASING POST-FILTER
The SAA4978H contains an embedded 80C51 microcontroller core including a 1 kbyte RAM and a 32 kbyte ROM. It also includes an I2C-bus user control interface. For development reasons an external ROM can be accessed with 64 kbyte maximum size. An external emulator can be connected. The main difference to most existing 80C51 derivatives is: * 768 byte auxiliary RAM from which 128 bytes can be accessed as subtitle RAM * Interrupt vector address for the I2C-bus is 33H * On-chip ROM code protection * SNERT at 1 or 2 Mbaud with additional Sample Frequency Registers (SFRs) instead of UART * Host interface containing all control registers access e.g. via MOVX instruction. 7.3.7 BOARD LEVEL TESTABILITY
A 3rd-order linear phase filter is applied to each of the Y, U and V channels. It provides a notch on fclk (32 MHz at Y, U and V) to strongly prevent aliasing to low frequencies, which would be most disturbing. The filters can be bypassed if external filtering with other characteristics is desired. Bandwidth and gain accuracy are given in Chapter 11. 7.3.3 PLL
The PLL consists of a ring oscillator, Discrete Time Oscillator (DTO) and digital control loop. The PLL characteristic is controlled by means of the microcontroller. 7.3.4 SNERT
A SNERT interface is built-in to transform the parallel data from the microcontroller into 1 or 2 Mbaud switchable SNERT data. This interface is also capable of reading data from the SNERT bus should it be required to access read registers. The read or write operation must be set by the microcontroller. When writing to the bus, 2 bytes are loaded by the microcontroller; one for the address, the other for the data. When reading from the bus, 1 byte is loaded by the microcontroller for the address, the received byte is the data from the addressed SNERT location. The SNERT interface replaces the standard UART interface. In contrast to the 80C51 UART interface there are additional control registers, other I/O pads and no byte separation time between address and data. After power-on reset the 1 Mbaud mode is active. Switching baud rate during transmission should be avoided. 7.3.5 PSP
Boundary scan test is implemented, according to "IEEE standard 1149.1". The boundary scan affects all digital pins and will cover all connections from the SAA4978H to other ICs that are also equipped with BST. The connectivity of the analog YUV input/output pins can also be tested with the use of BST. The digital outputs UVAL, UVA0, UVA1, UVA2, UVA3, YAL, UVCL, UVC0, UVC1, UVC2, UVC3, YCL, WEA, WEC and IEC can be set in 3-state mode if not connected in the application. This means that these outputs with index 0 to 3 are set in 3-state if 4 : 1 : 1 is chosen, and the outputs with index L are set in 3-state if 8 bits output is chosen. 7.3.8 POWER-ON RESET
All digital blocks except PLL are reset by a HIGH level at the reset pin. Only the watchdog counter is reset by the falling edge of the reset pulse. The PLL needs no reset. The frequency guard generates a single reset pulse with a duration of 0.875 ms when the actual frequency enters the desired range of 14 to 18 MHz. If the frequency leaves this range then no reset pulse is generated.
For dynamically changing data such as timing signals, the programmable signal positioner generates them on the basis of parameters sent by the microcontroller. For the reset function of the microcontroller, a watchdog timer is also built-in that creates a reset pulse unless it is triggered by a change in the Bone signal within a preset time (1.05 s).
1999 May 03
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This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 17 Philips Semiconductors 8 CONTROL REGISTER DESCRIPTION
Picture Improved Combined Network (PICNIC)
NAME
ADDRESS HEX
READ/ DOUBLE 876543210 WRITE BUFFERED(1)
DESCRIPTION
Clamp registers (clamp position in steps of one pixel, only first quarter of line available) CLAMP_START CLAMP_STOP AGC AGC_GAIN_Y AGC_GAIN_U AGC_GAIN_V Overflow detection control YUV_SELECT OVERFLOW_11_HIGH OVERFLOW_11_LOW OVERFLOW_10_HIGH OVERFLOW_10_LOW OVERFLOW_01_HIGH OVERFLOW_01_LOW Digital front-end DFRONTEND_CONTROLS1 U_CLAMP_COR_FVAL 306 write XXXXXXXX X X X U clamp correction value (twos complement) used in external correction mode XXX V clamp correction value (twos complement) used in external correction mode 305 300 301 302 303 304 305 write read read read read read read E E E E E E X X select ADC (Y, U, V, V) X X X X X X X X read HIGH byte level 11 X X X X X X X X read LOW byte level 11 X X X X X X X X read HIGH byte level 10 X X X X X X X X read LOW byte level 10 X X X X X X X X read HIGH byte level 01; underflow/overflow X X X X X X X X read LOW byte level 01; underflow/overflow 302 303 304 write write write X X X X X X X X X set Y gain (-3 to +6 dB) X X X X X X X X X set U gain (-3 to +6 dB) X X X X X X X X X set V gain (-3 to +6 dB) 300 301 write write X X X X X X X X clamp start position X X X X X X X X clamp stop position
V_CLAMP_COR_FVAL
Product specification
UV_COR_MODE DFRONTEND_CONTROLS2 UV_TAU Y_DELAY 307 write
XX XXXXXXX
UV clamp correction mode (internal, external, keep, keep) X X select UV clamp time constant (4, 9, 19 and 39 lines) XX select Y delay (-1, 0, 1, 2)
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 18 Bus A output control BUS_A_CONTROL1 Y_BUS_A_8BIT_ROUND Y_BUS_A_DITHER XXX 30D write XXXXXXXX X X Y bus A (9-bit rounded, 9-bit rounded, 8-bit dithered, 8-bit truncated) dithering mode on Y bus A (F1L1, F1L2, F1L1,F1L2, F2L1, F2L2, F4L1, F4L2) select 4 : 2 : 2 output format (4 : 1 : 1, 4 : 2 : 2) select UV coring mode (off, 0.5, 1.0, 1.5 LSB) Product specification SEL_422_OUT UV_CORING BUS_A_CONTROL2 UV_BUS_A_8BIT_ROUND 30E write XX XXXXXXX UV_BUS_A_DITHER Philips Semiconductors NAME MFF_WIDTH DFRONTEND_CONTROLS3 NLP_L_AD NLP_U_AD NOTCH ACT_VIDEO_WINDOW_H_START ACT_VIDEO_WINDOW_V_START CLAMP_U_ERROR 309 30B 306 write write write write read S ACT_VIDEO_WINDOW_H_LENGTH 30A ACT_VIDEO_WINDOW_V_LENGTH 30C X XXXXXXXX XXXXXXXX XXXXXXXXX X X X X X X X X X not double buffered for PSP (WEA) 0 X X X X X X X clamp offset in U (twos complement; gain 16) used in internal correction mode 0 X X X X X X X clamp offset in V (twos complement; gain 16) used in internal correction mode XX 308 write ADDRESS HEX READ/ DOUBLE 876543210 WRITE BUFFERED(1) XXX XXXXX X X input settings (0, 116, 216, 316) input settings (0, 14, 12, 12) select notch (off, on)
Picture Improved Combined Network (PICNIC)
DESCRIPTION select MFF width (0, 3, 5, 7, 9, 9, 9 and 9 samples)
CLAMP_V_ERROR
307
read
X
SAA4978H
X X UV bus A (9-bit rounded, 9-bit rounded, 8-bit dithered, 8-bit rounded) XXX dithering mode on UV bus A (F1L1, F1L2, F1L1, F1L2, F2L1, F2L2, F4L1, F4L2)
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Picture Improved Combined Network (PICNIC)
DESCRIPTION force bus A output to 3-state including WEA (off, on) WEA definition (prequalifier, qualifier)
SEL_DOUBLE_CLOCK SEL_ASYNCHRONOUS UV_INV WE_B_QUALIFIER INV656 TBC/SRC control C0 310 write S
X X X X X X X X X control of compression/expansion at line centre (twos complement: -256 to +255) X X X X X X X X control of compression/expansion at line edges (twos complement: -128 to +127) X X X X X X X X horizontal shift (bits 15 to 8) X X X X X X X X horizontal shift (bits 7 to 0) X X X X X X X X horizontal data path delay (bits 7 to 0) XXXXXXX X X X X X horizontal data path delay (bits 12 to 8) XX skew multiply factor (off, 1, undefined, -1) Product specification
C2
311
write
S
H_SHIFT_HIGH H_SHIFT_LOW H_DATAPATH_DELAY H_DATAPATH_DELAY_SKEW H_DATAPATH_DELAY_MSB SKEW_MULT
312 313 314 315
write write write write
S S S S
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 20 Philips Semiconductors NAME Noise estimator LIMERIC_THR_UP LIMERIC_WANTED_VALUE LIMERIC_TASTE_AND_COMP TASTE_VALUE COMPENSATION_VALUE LIMERIC_LB_DETAIL LIMERIC_UB_DETAIL LIMERIC_YP_AND_OVLPL OVERLAP_VALUE PREFILTER_SCALING SOB_NEGLECT X XX 319 31A 31B write write write S S S XXXX 316 317 318 write write write S S X X X X X X X X threshold to define the weight factor of considered pixels X X X X X X X X sensitivity of noise estimator XXXXXXXX X X X X taste value compensation value (twos complement) ADDRESS HEX READ/ DOUBLE 876543210 WRITE BUFFERED(1)
Picture Improved Combined Network (PICNIC)
DESCRIPTION
X X X X X X X X bottom limit of detail counter X X X X X X X X top limit of detail counter XXXXXXXX X X X X overlap level for noise estimator (0 to 15) luminance prefilter scaling (1, 12, 14, off) neglects the Sum Over a Block value of those blocks that contain values towards black and white; (use, neglect) = (measure except around black and white level, measure everywhere number of bits at input of NE block (9, 8)
INPUT8BIT NEST NEST_FILT DETAIL_CNT_H DETAIL_CNT_L 308 309 30A 30B read read read read E E E E
X
0 0 0 0 X X X X noise estimator value X X X X X X X X filtered noise estimator value X X X X X X X X number of details detected in field (HIGH byte) X X X X X X X X number of details detected in field (LOW byte) Product specification
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 21 THRESHOLD_LSB NBR_EVENTS TOT_COR_H TOT_COR_M TOT_COR_L 30C 30D 30E 30F read read read read E E E E XX Line memory and noise reduction (LIMERIC) control LIMERIC_CONTROL N_DIST PC_DIST PE_DIST XX XX 320 write S Philips Semiconductors NAME ADDRESS HEX READ/ DOUBLE 876543210 WRITE BUFFERED(1)
Picture Improved Combined Network (PICNIC)
DESCRIPTION
Clamp noise reduction (CLINIC) control CLINIC_CONTROL K_SCALE K_ONE CLINIC_OFF DITHER CLINIC_MAX_DIFF 31D write S X X X 31C write S XXXXXX X X X select K scale (4, 2, 1, 12, 14, 18, 116, 132) select K is 1 versus adaptive (adaptive, K = 1) CLINIC function off (on, off) dither on (off, on)
X X X X X X X X maximum difference allowed between actual and stored segment value (bits 9 to 2) X X X X X X X X threshold to define motion in segments (bits 9 to 2) XXXX X X maximum difference allowed between actual and stored segment value (bits 1 and 0) threshold to define motion in segments (bits 1 and 0)
CLINIC_THRESHOLD CLINIC_DIF_AND_THR_LSB MAX_DIFF_LSB
31E 31F
write write
S S
X X X X X X X X number of events per field with motion above threshold X X X X X X X X accumulated absolute clamp correction in field (bits 18 to 11) X X X X X X X X accumulated absolute clamp correction in field (bits 10 to 3) 0 0 0 0 0 X X X accumulated absolute clamp correction in field (bits 2 to 0) Product specification
SAA4978H
XXXXXXXX X X select n_dist (2, 4, 8, 9) select pc_dist (1, 2, 3, 4) select pe_dist (5, 6, 7, 8)
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Picture Improved Combined Network (PICNIC)
DESCRIPTION weave on (off, on) select threshold from estimator versus threshold from microcontroller (estimator, microcontroller)
Band split peaking and coring PEAKING_CONTROL1 2D_PEAK_COEF CORE_THR V_GAINSTR 322 write S XXXX 321 write S XXXX XXX X X X 2D peaking coefficient (0, 24, 34, 44, 54, 64, 74, 84) coring threshold (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 LSB) X X X vertical peaking (0, 18, 28, 38, 48, 58, 68, 78) X X X X X X X X mean vertical energy measured in one field (bits 15 to 8) X X X X X X X X mean vertical energy measured in one field (bits 7 to 0) X X X X X X X X maximum vertical peak energy measured in one field
1 1 1 1
Noise reduction energy measurement VHF_ENERGY_SUM_H VHF_ENERGY_SUM_L VHF_ENERGY_MAX Black bar position and control BBD_FIRST_VIDEOLINE1 BBD_LAST_VIDEOLINE1 BBD_FIRST_VIDEOLINE2 BBD_LAST_VIDEOLINE2 BBD_WINDOW_H_START BBD_WINDOW_H_STOP BBD_WINDOW_V_START BBD_WINDOW_V_STOP 313 314 315 316 323 324 325 326 read read read read write write write write E E E E S S S S XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXXX XXXXXXXXX
2 number of first line after black bar having video 2 number of last line before black bar having video 2(number + 1) of first line after black bar having video 2(number + 1) of last line before black bar having video
310 311 312
read read read
E E E
Product specification
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 23 SPLIT_POSITION HISTOGRAM_CONTROL1 HISTO_GAIN NOISE_RED FILTER_1_ON FILTER_2_ON RESERVED WRITE ADDRESS YUV_IN_CONTROL ROUND RATIO_LIMIT UV_POS UV_GAIN HGM_WINDOW_H_START 331 write S XX X X 32F 330 write write S XXX XX X rounding versus truncating (truncated, rounded) select UV ratio 128 versus 64 (64, 128) follow if dy > 0 versus follow dy (follow dy, follow if dy > 0) UV gain (0, 12, 1, 2) X X X 32D 32E write write S Philips Semiconductors NAME BBD_LOGO_LENGTH BBD_SLICE_LEVEL1 BBD_SLICE_LEVEL2 Histogram control BLACK_OFFSET LUT_DATA 32A 32B write write S X X X X X X X X definition of DC shift in Y (twos complement) X X X X X X X X transfer of 32 bytes that define the Y transfer LUT from microcontroller to histogram (twos complement). The first write after a field reset resets the write pointer; subsequent write operations increment the write pointer. S X X X X X X X X if Yn - Yn - 1 > threshold then Yn is added to the histogram X X X X X X X X position of split point in steps of 4 pixels (left side unprocessed) X X X X X X X not double buffered X X X X histogram gain (0 to 15) noise reduction on 1 : 2 : 1 filter on (off, on) 1 : 0 : 2 : 0 : 1 filter on (off, on) ADDRESS HEX 327 328 329 READ/ DOUBLE 876543210 WRITE BUFFERED(1) write write write S S S
Picture Improved Combined Network (PICNIC)
DESCRIPTION
X X X X X X X X number of non-black samples permitted in a black bar line XXXXXXXX XXXXXXXX
1 1 2 threshold to detect black (detector 1) 2 threshold to detect black (detector 2)
THRESHOLD_HIS
32C
write
Product specification
SAA4978H
X X X X X X X X start of horizontal histogram window
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 24 Philips Semiconductors NAME HGM_WINDOW_H_STOP HGM_WINDOW_V_START HGM_WINDOW_V_STOP Histogram outputs HISTOGRAM_DATA 317 read X X X X X X X X Histogram read command. The first read after a field reset resets the read pointer; subsequent read operations increment the read pointer. E E E E E E E E X X X X X X X X minimum Y value in previous field X X X X X X X X maximum Y value in previous field X X X X X X X X minimum U value in previous field X X X X X X X X maximum U value in previous field X X X X X X X X minimum V value in previous field X X X X X X X X maximum V value in previous field X X X X X X X X maximum value in histogram of previous field X X X X X X X X black level indication (filtered Y_MIN) ADDRESS HEX 332 333 334 READ/ DOUBLE 876543210 WRITE BUFFERED(1) write write write S S S
Picture Improved Combined Network (PICNIC)
DESCRIPTION
X X X X X X X X stop of horizontal histogram window X X X X X X X X X start of vertical histogram window X X X X X X X X X stop of vertical histogram window
Y_MIN Y_MAX U_MIN U_MAX V_MIN V_MAX MAX_HISTO_VALUE SMART_BLACK Subtitle control THRESHOLD_HIGH THRESHOLD_LOW HIGH_TIME LOW_TIME SUBTITLE_CONTROLS RESET_EVENTS EVENT_MODE
318 319 31A 31B 31C 31D 31E 31F
read read read read read read read read
335 336 337 338 339
write write write write write
X X X X X X X X maximum level required for valid event X X X X X X X X minimum level required for valid event X X X X X X X X minimum time above HIGH threshold required for valid event X X X X X X X X minimum time below LOW threshold required for valid event XXX X reset events (cumulative, reset) X select event versus between thresholds mode (within thresholds, events) select `every field' versus `bleed' (bleed, every field) Product specification
SAA4978H
RESET_PEAK SUBT_WINDOW_H_START 33A write
X XXXXXXXX
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1 2 peak value of Y within the event window
Picture Improved Combined Network (PICNIC)
DESCRIPTION
RESERVED READ ADDRESS PEAK_Y Bars control BAR_ARRAY
320 321
read read
33E
write
X X X X X X X X Bar array write command. The first write after a field reset resets the write pointer; subsequent write operations increment the write pointer (see also BAR_ARRAY_RESOLUTION). S S S S X X X X X X X X display bar luminance level X X X X X X X X display bar U level (twos complement) X X X X X X X X display bar V level (twos complement) X X X X X X X X horizontal start position of the display bars (see also BAR_ARRAY_RESOLUTION) X X X X X X X X vertical start position of the display bars X X X X X X X X the width of each bar in number of lines (see also BAR_ARRAY_RESOLUTION) X X X X X X X X the number of lines between two bars (see also BAR_ARRAY_RESOLUTION) XXX X select bar array on (off, on)
BAR_ARRAY_Y BAR_ARRAY_U BAR_ARRAY_V BAR_ARRAY_H_START
33F 340 341 342
write write write write
BAR_ARRAY_V_START BAR_ARRAY_WIDTH
343 344
write write
S S
BAR_ARRAY_SPACE
345
write
S
Product specification
SAA4978H
BAR_ARRAY_CONTROL BAR_ARRAY_ON
346
write
S
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Picture Improved Combined Network (PICNIC)
DESCRIPTION select bar array resolution (BAR_ARRAY_H_START x 4, BAR_ARRAY_WIDTH x 2, BAR_ARRAY_SPACE x 2, BAR_ARRAY x 4, BAR_ARRAY_H_START x 2, BAR_ARRAY_WIDTH x 1, BAR_ARRAY_SPACE x 1, BAR_ARRAY x 2) select mashing versus superimpose (superimpose, mashing)
BAR_ARRAY_TRANS Bus C output control BUS_C_CONTROL1 SEL422OUT UV_BUS_C_8BIT_ROUND 347 write S
X
XXXXXXXX X select 4 : 2 : 2 output (4 : 1 : 1, 4 : 2 : 2) overridden by DPCM XX UV bus C (9-bit rounded, 9-bit rounded, 8-bit dithered, 8-bit truncated) multi-PIP mode (off, 2 x 2, 3 x 3, 4 x 4); see also memory write control dither line and field phase (f1l1, f1l2, f1l1, f1l2, f2l1, f2l2, f4l1, f4l2)
Product specification
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 27 Philips Semiconductors NAME Field memory control WE_WINDOW_H_START WE_WINDOW_H_STOP ACQ_EN_WINDOW_V_START ACQ_EN_WINDOW_V_STOP IE_WINDOW_H_START IE_WINDOW_H_STOP WE_IE_SHIFT WE_C_SHIFT IE_C_SHIFT CHOP_CYCLE RE_WINDOW_H_START RE_WINDOW_H_STOP RE_WINDOW_V_START RE_WINDOW_V_STOP Bus D input control BUS_D_CONTROL SEL_INPUT_FORMAT 355 write S X XX X X select input format (4 : 2 : 2 external, 4 : 1 : 1 external, 4 : 2 : 2 internal, DPCM external) Product specification X 356 357 358 359 write write write write XXXXXXXX XXXXXXXX XXXXXXXXX XXXXXXXXX select undither active (off, on) 350 351 352 353 354 write write write write write XX 349 34A 34B 34C 34D 34E 34F write write write write write write write X X X X X X X X start of horizontal write enable window X X X X X X X X stop of horizontal write enable window X X X X X X X X X start of vertical write and input enable window X X X X X X X X X stop of vertical write and input enable window X X X X X X X X start of horizontal input enable window X X X X X X X X stop of horizontal input enable window XXXX X X fine shift of WEC (0, 1, 2, 3 pixels) fine shift of IEC (0, 1, 2, 3 pixels) X X chop cycle of WEC and IEC (1, 12, 13, 14) X X X X X X X X define start of horizontal read enable window X X X X X X X X define stop of horizontal read enable window X X X X X X X X X define start of vertical read enable window X X X X X X X X X define stop of vertical read enable window ADDRESS HEX READ/ DOUBLE 876543210 WRITE BUFFERED(1)
Picture Improved Combined Network (PICNIC)
DESCRIPTION
UNDITHER BE_WINDOW_H_START BE_WINDOW_H_STOP BE_WINDOW_V_START BE_WINDOW_V_STOP
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 28 Philips Semiconductors NAME CTI control DBACKEND_CONTROLS1 CTI_SEPARATE CTI_PROTECTION CTI_GAIN CTI_FILTER_ON DBACKEND_CONTROLS2 CTI_LIMIT CTI_SUPERHILL CTI_DDX_SEL CTI_SUPERHILL NLP_DA NLP_L_DA NLP_U_DA Dynamic peaking and coring PEAKING_CONTROL2 ALPHA BETA DELTA LUTREGA LEVEL1 LEVEL2 LEVEL3 LEVEL4 LUTREGB 35F write S XXX XX XX 35E write S XX XXX 35D write S XXXXXXXX X X X value (0, 116, 216, 316, 416, 516, 616, 816) value (0, 116, 216, 316, 416, 516, 616, 816) value (0, 14, 12, 1) XX 35C write XXXX XXXX X X output settings (0, 18, 28, 38) output settings (0, 14, 12, 12) X X 35B write X XXXXXXXX X X limit CTI range (0, 4, 8, 12) select super hill protection (off, on) select first differentiating filter (-1 0 0 1, -1 -2 -1 1 2 1) hill detection threshold (0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15) XXX X 35A write XXXXXX X separate U and V processing (linked, separate) select hill protection (off, on) CTI gain (0, 18, 28, 38, 48, 58, 68, 78) post-filter on (off, on) ADDRESS HEX READ/ DOUBLE 876543210 WRITE BUFFERED(1)
Picture Improved Combined Network (PICNIC)
DESCRIPTION
X X X X X X X X programmable coring replacement values for luminance levels 1 to 4 X level 1 (0, 1) level 2 (0, 1, 2, 3) level 3 (0, 1, 2, 3) level 4 (0, 1, 2, 3, 4, 5, 6, 7) Product specification
SAA4978H
X X X X X X X X programmable coring replacement values for luminance levels 5 to 7
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Picture Improved Combined Network (PICNIC)
DESCRIPTION
X X X level 5 (0, 1, 2, 3, 4, 5, 6, 7) level 6 (0, 1, 2, 3, 4, 5, 6, 7) level 7 (4, 5, 6, 7)
X X X X X X X X local energy above coring-threshold switches off coring XXXXXXXX X X X value (0, 116, 216, 316, 416, 516, 616, 816) negative gain value (0, 14, 12, 1) coring (coarse, fine) in accordance with LUTREGA and LUTREGB; see Fig.13 energy select (high x 4, mid, low, high)
ENERGY_SEL ENERGY_SELECT_V_START ENERGY_SELECT_V_STOP RESERVED READ ADDRESS RESERVED READ ADDRESS ENERGY_MAX 362 363 322 323 324 write write read read read E E E
XX
X X X X X X X X X start of vertical energy select window X X X X X X X X X stop of vertical energy select window XXXXXXXX XXXXXXXX X X X X X X X X maximum peak energy measured in one field
Blanking control (definition of blanking window) BLANKING_WINDOW_H_START BLANKING_WINDOW_H_STOP BLANKING_WINDOW_V_START BLANKING_WINDOW_V_STOP Border control BORDER_SIDE_H_START BORDER_SIDE_H_STOP BORDER_SIDE_V_START BORDER_SIDE_V_STOP BORDER_BAR_H_START BORDER_BAR_H_WIDTH BORDER_BAR_V_START 368 369 36A 36B 36C 36D 36E write write write write write write write X X X X X X X X start of right border Product specification X X X X X X X X end of left border X X X X X X X X X start of lower border X X X X X X X X X stop of upper border X X X X X X X X start of first horizontal bar X X X X X X X X width of horizontal bars X X X X X X X X X start of first vertical bar 364 365 366 367 write write write write XXXXXXXX XXXXXXXX XXXXXXXXX XXXXXXXXX
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 30 PLL_OFF PLL_OPEN DO_SNAP PLL_IDTO(15-8) PLL_IDTO(7-0) PLL_SKEW_DELAY 377 378 379 write write write V V V X X X PLL_PE_MAX(15-8) PLL_PE_MAX(7-0) PLL_PE_MIN(15-8) 325 326 327 read read read V V V Philips Semiconductors NAME BORDER_BAR_V_WIDTH BORDER_REPEAT_H BORDER_REPEAT_V BORDER_Y BORDER_U BORDER_V PLL PLL_CK_AND_CD PLL_CK PLL_CD PLL_IDTO_PLUS_VARIOUS PLL_IDTO(18-16) 376 write V 375 write V V V XXX XXX XXX X X X increment offset for DTO bits 18 to 16 (twos complement; bit 18 is the sign bit) PLL off; keep output frequency (off, on) PLL open loop mode (closed, open) do snapshot XXXXXXXX X X X X X K factor control (0 to 31) damping control (0 to 7) ADDRESS HEX 36F 370 371 372 373 374 READ/ DOUBLE 876543210 WRITE BUFFERED(1) write write write write write write
Picture Improved Combined Network (PICNIC)
DESCRIPTION
X X X X X X X X X width of vertical bars X X X X X X X X horizontal repeat value X X X X X X X X X vertical repeat value X X X X X X X X Y value of sides and bars X X X X X X X X U value of sides and bars (twos complement) X X X X X X X X V value of sides and bars (twos complement)
X X X X X X X X increment offset for DTO bits 15 to 8 X X X X X X X X increment offset for DTO bits 7 to 0; transfers all bits (18 to 0) X X X skew transferred: 512 x (1 + PLL_SKEW_DELAY) clocks after HREF; PLL_SKEW_DELAY (0 to 7) Product specification X X X X X X X X maximum phase offset during field HIGH byte X X X X X X X X maximum phase offset during field LOW byte; transfers all bits (15 to 0) X X X X X X X X minimum phase offset during field HIGH byte
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 31 PLL_CKA_VALUE PLL_ADAPT_STATUS RESERVED READ ADDRESS Read registers PSP HA_VALUE VA_VALUE HD_VALUE VD_VALUE PIP_RISING_EDGE_POS PIP_FALLING_EDGE_POS INTR_0_SOURCE 333 334 335 336 337 338 339 read read read read read read read X X X X X X X X available after VA or COPY_VALUE_STROBE X X X X X X X X as HA_VALUE; bit 8 in register VARIOUS_BITS X X X X X X X X available after VD or COPY_VALUE_STROBE Product specification X X X X X X X X as HD_VALUE; bit 8 in register VARIOUS_BITS XXXXXXXX XXXXXXXX 0 0 0 0 0 0 X X interrupt read; register reset after read 330 331 332 read read read V V Philips Semiconductors NAME PLL_PE_MIN(7-0) PLL_PE_SUM(15-8) PLL_PE_SUM(7-0) PLL_PE_SABS(15-8) PLL_PE_SABS(7-0) ADDRESS HEX 328 329 32A 32B 32C READ/ DOUBLE 876543210 WRITE BUFFERED(1) read read read read read V V V V V
Picture Improved Combined Network (PICNIC)
DESCRIPTION
X X X X X X X X minimum phase offset during field LOW byte; transfers all bits (15 to 0) X X X X X X X X accumulated phase offset during field HIGH byte X X X X X X X X accumulated phase offset during field LOW byte; transfers all bits (15 to 0) X X X X X X X X accumulated absolute phase offset during field HIGH byte X X X X X X X X accumulated absolute phase offset during field LOW byte; transfers all bits (15 to 0) 0 0 0 0 X X X X increment offset bits 19 to 16 (twos complement; bit 19 is the sign bit) X X X X X X X X increment offset bit HIGH byte X X X X X X X X increment offset bit LOW byte; transfers all bits (19 to 0) 0 0 0 X X X X X actual K value 0 0 0 0 0 0 0 X PLL adaptive status (locked, unlocked)
PLL_INC_OFFSET(19-16)
32D
read
V
PLL_INC_OFFSET(15-8) PLL_INC_OFFSET(7-0)
32E 32F
read read
V V
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 32 Philips Semiconductors NAME VA_INTR_ACTIVE WE_INTR_ACTIVE VARIOUS_BITS VA_VALUE_MSB VD_VALUE_MSB Various PSP control VA_SYNC_WINDOW_START VA_SYNC_WINDOW_STOP VA_INC_HOR_POS HREF_EXT_START HREF_EXT_STOP INTR_AND_SYNC_ENABLE INTR_VA_ENABLE INTR_WE_ENABLE INTR_VD_ENABLE HD_CNTR_RST_BY_HDREF DIVIDE_VD_INC SEL_HA_CLAMP INTR_VA_DELAY HD_START HD_STOP VD_HOR_POS H_EXT_POS 380 381 382 383 384 write write write write write X X X X X 37A 37B 37C 37D 37E 37F write write write write write write X X X X X X X X X start of vertical VA_SYNC enable window X X X X X X X X X stop of vertical VA_SYNC enable window X X X X X X X X horizontal position of VA_COUNTER clock X X X X X X X X start HREFEXT pulse X X X X X X X X stop HREFEXT pulse XXX XXX X VA interrupt enable (disabled, enabled) WE interrupt enable (disabled, enabled) VD interrupt enable (disabled, enabled) HD counter reset from HD_REF (no reset, reset by HD_REF) divide VD_INC by 2 (100 Hz, progressive scan mode) select clamp-counter reset (HA_REF, HA) Product specification X 33A read X 000000XX X MSB of VA MSB of VD ADDRESS HEX READ/ DOUBLE 876543210 WRITE BUFFERED(1)
Picture Improved Combined Network (PICNIC)
DESCRIPTION
X VA interrupt active (not active, active) WE interrupt active (not active, active)
X X X X X X X X X delay in number of lines delay at pin 157 caused by VA X X X X X X X X start HD pulse X X X X X X X X stop HD pulse X X X X X X X X horizontal phase of VD X X X X X X X X HD counter length
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 33 Philips Semiconductors NAME INTR_VD_DELAY PLL_OFF_START PLL_OFF_STOP DISPLAY_CONTROL RE_SHIFT ENABLE_RESET_BLANK PIXEL_REPETITION ENABLE_BORDER_V_BAR ENABLE_BORDER_V_SIDE ENABLE_BORDER_H_BAR ENABLE_BORDER_H_SIDE RESERVED WRITE ADDRESS ACQ_WINDOWS_RESET COPY_VALUE_STROBE TRIGGER_FLYBACK TRIGGER_SCAN COUNTER_VD_RESET INTR_1_RESET DISPLAY_WINDOWS_RESET SEL_1FH BUS_B_VREF NRPXDIV4 389 38A 38B 38C 38D 38E 38F 390 391 392 393 write write write write write write write write write write write S TRIGGER to reset acquisition windows TRIGGER to copy register values TRIGGER to set VD output TRIGGER to reset VD output TRIGGER to reset VD counter TRIGGER to reset interrupt 1 TRIGGER to reset display windows X select back-end clock at 16 MHz for 1fH processing (32 MHz, 16 MHz) X X X X X X X X X vertical start field reference for bus B XXXXXXXX
1 4 of horizontal length of video data in data path
ADDRESS HEX 385 386 387 388
READ/ DOUBLE 876543210 WRITE BUFFERED(1) write write write write
Picture Improved Combined Network (PICNIC)
DESCRIPTION
X X X X X X X X X value of COUNTER_VD that initiates interrupt 1 X X X X X X X X X vertical start of PLL_OFF window X X X X X X X X X vertical stop of PLL_OFF window XXXXXXXX X X RE pixel shift (0, 1, 2, 3) X X X X X X enable blank reset (disabled, enabled) enable pixel repetition (disabled, enabled) enable vertical bars (disabled, enabled) enable vertical sides (disabled, enabled) enable horizontal bars (disabled, enabled) enable horizontal sides (disabled, enabled)
Product specification
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 34 Philips Semiconductors NAME Testing RESET_CONTROL FIELD_RESET TEST_Y_IN_D TEST_UV_IN_D Analog blocks ANASWITCH CLAMP_ACTIVE STDIFF_CONV STDIFF_CONV_AGC STDIFF_CONV_AGC_FILTER FRONTEND_TO_OUTPUT ATT_OUT ATT_RECONSTRUCT_OUT FRONTEND_TO_BACKEND RESERVED WRITE ADDRESS RESERVED WRITE ADDRESS TM_AD_DA TM_ADDA2 TM_ADDA1 TM_AD2DA X X 396 397 398 write write write X XXXX X X X X test mode AD, DA blocks X ADC and DAC test ADC and DAC test direct bypass from ADC to DAC Product specification X X X X X X 395 write X X X X X X X X test register for analog functions; normal application mode: 49H X clamp active single to differential converter single to differential converter and AGC single to differential converter, AGC and filter front-end to output attenuator to output attenuator and reconstruction filter to output front-end to back-end 33B 33C read read 394 write X X X X X X X X X X test receive register at bus D; Y input X X X X X X X X test receive register at bus D; UV input ADDRESS HEX READ/ DOUBLE 876543210 WRITE BUFFERED(1)
Picture Improved Combined Network (PICNIC)
DESCRIPTION
SAA4978H
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1999 May 03 35 Philips Semiconductors NAME ADDRESS HEX READ/ DOUBLE 876543210 WRITE BUFFERED(1)
Picture Improved Combined Network (PICNIC)
DESCRIPTION
SNERT control (these registers are implemented as special function register, they have a HEX address outside the normal control register range) SNCON TRM REC MB2 SNADD SNWDA SNRDA Note 1. Blank means not double buffered; E means double buffered and data available at end of active video; S means double buffered and data clocked in at start of active video; V means double buffered and data valid at start of VA. 99 9A 9B 98 read/ write read read/ write read/ write write write read X X X 0 0 0 0 0 X X SNERT control register (reset on bit 1 of register $E8: power-on reset) X SNERT transmit busy flag SNERT receive busy flag SNERT baud rate (1 MHz, 2 MHz)
X X X X X X X X address of SNERT message to be transmitted X X X X X X X X data of SNERT message to be transmitted X X X X X X X X data from SNERT bus after a completed reception
Product specification
SAA4978H
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDA VDDD; VDDO VDDA - DDD VDDA - DDO VI Vi Tstg Tj PARAMETER analog supply voltage digital supply voltage supply voltage difference between analog and digital supply voltages supply voltage difference between analog and output supply voltages analog input voltage storage temperature operating junction temperature -0.5 -0.5 -0.5 -0.5 MIN. +6 +6 +0.5 +0.5 +5.5 VDDA + 0.3 +150 125 MAX.
SAA4978H
UNIT V V V V V V C C
input voltage for all digital input and digital I/O pins -0.5 -0.3 -55 0
10 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) Rth(j-c) PARAMETER thermal resistance from junction to ambient thermal resistance from junction to case CONDITIONS in free air VALUE 25 2 UNIT K/W K/W
1999 May 03
36
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SAA4978H
11 CHARACTERISTICS VDDD = VDDA = 3.3 V; AGC at 0 dB; Tamb = 25 C; nominal parameter settings: 2fH/100 Hz mode; features transparent; equalized frequency response test signal: EBU colour bar 100/0/75/0 "CCIR471-1"; unless otherwise specified. SYMBOL Supplies VDDD VDDA VDD(I/O) VDDO Dissipation Ptot YAGC UAGC VAGC EG(YUV)all EG(UV)i total power dissipation - - 1.6 W - - - % % digital supply voltage analog supply voltage microcontroller I/O supply voltage digital supply voltage for outputs 3.0 3.15 3.0 3.0 3.3 3.3 - 3.3 3.6 3.45 5.5 3.6 V V V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
YUV input processing (including AGC) Y AGC setting to obtain full ADC range U AGC setting to obtain full ADC range V AGC setting to obtain full ADC range Vi(Y)(b-w) = 1.0 V (p-p); note 1 117 132 136 132 - 1 148 151 148 +5.6 3.2
Vi(U) = 1.33 V (p-p); note 1 120 Vi(V) = 1.05 V (p-p); note 1 117 -5.6 -
overall input to output gain f = 0 to 2.5 MHz (analog error between Y, U and V filters off) gain error between U and V inputs overall gain error between U and V filtered gain error between U and V input overall filtered gain error between U and V input capacitance input leakage current clamp not active; 0 < Vi < VDDA + 0.3 f = 0 to 2.5 MHz (analog filters off) from input to digital domain f = 0 to 2.5 MHz (analog filters off) from input to output f = 0 to 1.25 MHz (analog filters on) from input to digital domain f = 0 to 2.5 MHz (analog filters on) from input to output
EG(UV)all
-
1.2
4.0
%
EG(f)(UV)i
-
2
6.4
%
EG(f)(UV)all
-
2.5
8
%
Ci ILI
- - 9
7 - 9.5
15 100 10
pF nA dB
GAGC(min-max) difference in gain between AGC minimum and maximum GAGC(acc) Gstep(AGC) AGC gain accuracy digital step resolution gain of AGC maximum gain variation per step
- -
9 -
- 0.4
bits %
1999 May 03
37
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SYMBOL ct PARAMETER crosstalk between inputs and outputs CONDITIONS f = 0 to 1 MHz; Zsource = 200 f = 1 to 5 MHz; Zsource = 200 Eclamp(stat)(Y) Eclamp(stat)(UV) Eclamp(dyn) Cclamp Rsource Iclamp(max) Tilt Vi(clamp)(Y) fi(s)(max) clk INL DNL SNR static clamp error in Y channel static clamp error in UV channel dynamic clamp error clamping capacitance source resistance maximum clamp current maximum drift in one line period Y input clamping voltage - - MIN. - - TYP.
SAA4978H
MAX. 50 44
UNIT dB dB
Input clamp processing (Y clamp level digital 32; U and V clamp level digital 0 in twos complement) -5.0 digital correction circuit off -3.0 average value (1 ) - 10 - -160 - over complete AGC range 600 - - - 22 - - - - - - - - 52 +2.0 +3.0 0.25 - 350 +160 0.25 - - 60 +2 +0.99 - LSB LSB LSB nF A LSB mV
Input transfer functions (sample rate 16 MHz; 9 bits); see Fig.7 maximum input sample frequency duty factor of (internal) clock cycle DC integral non linearity DC differential non linearity overall signal-to-noise ratio (no harmonics) from input to output differential phase in U and V differential gain in Y front-end differential phase in Y front-end supply voltage ripple rejection Y within 0.2 to 0.75 V Y within 0.2 to 0.75 V filters off; note 4 ramp input signal; AGC on; filters off ramp input signal; note 2 note 3 18 40 -2 -0.99 50 MHz % LSB LSB dB
diff(UV) Gdiff(Y) diff(Y) SVRR
- - - 35
1 - - -
2.5 1.5 1 -
deg % deg dB
PLL function (base frequency 32 MHz) line-line field-field funlock sigma value of line-to-line jitter sigma value of field-to-field jitter frequency in unlocked state locked to stable HA; note 5 locked to stable HA; note 5 - - 30.7 0.4 0.4 32 1.0 1.0 33.3 ns ns MHz
1999 May 03
38
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA4978H
MAX.
UNIT
YUV output processing; note 6; see Fig.6 Vo(Y)(b-w) Vo(U)(p-p) Vo(V)(p-p) EG(UV)o Y black-to-white output voltage U output voltage (peak-to-peak value) V output voltage (peak-to-peak value) gain error between U and V output filtered gain error between U and V output output impedance Y super black level voltage at 0 Y super white (headroom) voltage at 1023 Y black level voltage at 288 Y white level voltage at 768 U voltage at 0 U voltage at 1023 V voltage at 0 V voltage at 1023 residual clock attenuation related to YOUT ZL = 10 k ZL = 10 k ZL = 10 k f = 0 to 2.5 MHz (analog filters off) from digital domain to output f = 0 to 2.5 MHz (analog filters on) from digital domain to output f = 0 to 10 MHz VbY = black level voltage VbY = black level voltage VbY = black level voltage VbY = black level voltage VbU = lower U voltage; note 7 VbV = lower V voltage; note 7 f = 32 or 16 MHz 0.96 1.27 1.01 - 1.00 1.33 1.05 - 1.04 1.38 1.09 2.5 V V V %
EG(f)(UV)o
-
-
5
%
Zo VY(d)(0) VY(d)(1023) VY(d)(288) VY(d)(768) VU(d)(0) VU(d)(1023) VV(d)(0) VV(d)(1023) res(clk)
65
75
85
VbY - 0.63 VbY - 0.6
VbY - 0.57 V
VbY + 1.47 VbY + 1.53 VbY + 1.59 V - VbY - V
VbY + 0.96 VbY + 1.0 - - - VbU VbV -
VbY + 1.04 V - - 40 V V dB
VbU + 1.43 VbU + 1.49 VbU + 1.55 V VbV + 1.13 VbV + 1.18 VbV + 1.23 V
Output transfer functions (sample rate 32 MHz; 10 bits) fclk(max) clk INL DNL maximum sample clock duty factor of clock cycle DC integral non linearity DC differential non linearity note 2 33.4 40 -2 -0.75 - - - - - 60 +2 +0.75 MHz % LSB LSB
Digital output bus A and C, WEA, WEC, IEC and HREFEXT (CL = 15 pF; IOL = 2 mA; RL = 2 k); timing referred to CLK16, HREFEXT is not a 3-state output VOH VOL IOZ Vext(OZ) td(o) 1999 May 03 HIGH-level output voltage LOW-level output voltage output current in 3-state mode external applied voltage in 3-state mode output delay time see Fig.4 39 -0.1 < Vo < VDDO + 0.1 2.4 - - - - - - - - - - 0.4 1.0 V V A
VDDO + 0.3 V 30 ns
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SYMBOL th(o) SR PARAMETER output hold time slew rate CONDITIONS see Fig.4 4 200 MIN. - 500 TYP.
SAA4978H
MAX. - 700
UNIT ns mV -------ns
Digital input bus B and D; timing referred to CLK32 for bus D and to CLK16, CLK32 or CLKAS for bus B (see Fig.4); the reference for bus B depends on the selected mode respectively single clock, double clock or asynchronous clock VIL VIH tsu(i) th(i) CLKAS VIL VIH th(i)(async) tL(min) tH(min) TCLKAS(min) LOW-level input voltage HIGH-level input voltage asynchronous input hold time minimum LOW time minimum HIGH time minimum period time the asynchronous clock may not be faster than CLK32 5 V tolerant 0 2.0 4 - - TCLK32 - - - - - - 0.8 5.5 - 10 10 - V V ns ns ns ns LOW-level input voltage HIGH-level input voltage input set-up time input hold time 5 V tolerant see Fig.4 see Fig.4 0 2.0 6 1 - - - - 0.8 5.5 - - V V ns ns
CLK16 and CLK32 (CL = 30 pF; IOL = 2 mA; RL = 2 k) VOL VOH to(r) to(f) tdHO thHO tdLO thLO LOW-level output voltage HIGH-level output voltage output rise time output fall time CLK16 HIGH transition delay time CLK16 HIGH transition hold time CLK16 LOW transition delay time CLK16 LOW transition hold time see Fig.4 see Fig.4 see Fig.5 see Fig.5 see Fig.5 see Fig.5 0 2.4 2 2 - 4 - 4 - - 3 3 - - - - 0.4 - 4 4 20 - 20 - V V ns ns ns ns ns ns
RED, HD and VD (CL = 15 pF; IOL = 2 mA; RL = 2 k); timing referred to CLK32; see Fig.4 VOH VOL td(o) th(o) SR HIGH-level output voltage LOW-level output voltage output delay time output hold time slew rate see Fig.4 see Fig.4 2.4 - - 4 200 - - - - 500 - 0.4 20 - 700 V V ns ns mV -------ns
1999 May 03
40
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SYMBOL PARAMETER CONDITIONS - see Fig.11 see Fig.12 see Fig.12 - - - - MIN. TYP.
SAA4978H
MAX. - - - 250 7
UNIT
Oscillator stage (operation with crystal or external clock) fosc CL34 CL35 Rser1(xtal) Cpar(xtal) oscillator frequency recommended load capacitor crystal series resistance crystal parallel capacitance 12 12 18 - - MHz pF pF pF
I2C-bus signal: SDA and SCL; note 8 VIH VIL VOL fSCL tHD;STA tSCLL tSCLH tSU;DAT tSU;DAT1 HIGH-level input voltage LOW-level input voltage LOW-level output voltage SCL clock frequency hold time START condition SCL LOW time SCL HIGH time data set-up time data set-up time (before repeated START condition) data set-up time (before STOP condition) set-up time repeated START set-up time STOP condition IOH = -0.06 mA IOL = 1.6 mA IOL = 3.0 mA 0.7VDDIO - - - 0.6 1.3 0.6 100 0.6 - - - - - - - - - - 0.3VDDIO 0.4 400 - - - - - V V V kHz s s s ns s
tSU;DAT2 tSU;STA tSU;STO
0.6 0.6 0.6
- - -
- - -
s s s
SNERT bus timing valid for both 1 and 2 Mbaud: SNDA and SNCL; see Fig.10 VOH VOL VIL VIH tsu(i)(SNCL) th(i)(SNCL) th(o) tsu(o) tdis(o) tcy(SNCL) tSNRSTH td(SNRST-DAT) HIGH-level output voltage LOW-level output voltage LOW-level input voltage HIGH-level input voltage input set-up time to SNCL input hold time to SNCL output hold time output set-up time output disable time SNCL cycle time SNRST pulse HIGH time delay SNRST pulse to data 2.4 - 0 2.0 80 0 50 260 - 500 500 200 - - - - - - - - - - - - - 0.4 0.8 5.5 - - - - 200 1000 - - V V V V ns ns ns ns ns ns ns ns
1999 May 03
41
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SYMBOL PARAMETER CONDITIONS MIN. - - TYP.
SAA4978H
MAX.
UNIT
HA and VA (horizontal and vertical sync input) VIL VIH tW(ALE) tAVLL tLLAX tLLIV tLLPL tW(PSEN) tPLIV tPXIX tPXIZ tAVIV tPLAZ LOW-level input voltage HIGH-level input voltage 0 2.0 - 17 20 - - - - 0 - - - 0.8 5.5 - - - 96 - - 60 - 30 128 10 V V
AC characteristics parallel bus: P0, P2, ALE and PSEN (external ROM access); see Fig.8 ALE pulse width address valid to ALE LOW address hold after ALE LOW ALE LOW to instruction input ALE LOW to PSEN LOW PSEN pulse width PSEN LOW to valid instruction input input instruction hold after PSEN input instruction float after PSEN address to valid instruction input PSEN LOW to address float 62.5 - - - 31.25 93.75 - - - - - ns ns ns ns ns ns ns ns ns ns ns
DC characteristics microcontroller pins: P0, P1, INT0, INT1, T0, T1, RSTW, RSTR, SNDA, SNCL, ALE, PSEN and EA VOH VOL VIL VIH ILI CI/O HIGH-level output voltage LOW-level output voltage LOW-level input voltage HIGH-level input voltage input leakage current pin capacitance IOH = -0.06 mA IOL = 1.6 mA 2.4 - 0 2.0 - - - - - - - - - 0.4 0.8 5.5 10 10 V V V V A pF
Analog Y, U and V input filters (3rd-order linear phase filter with notch at fCLK); see Fig.6 f(-3dB) (0.5) sb fnotch td(g) 3 dB down frequency attenuation at 12fCLK (8 MHz) stop band attenuation (after notch) notch frequency group delay tuned to 12fCLK 5.4 7 32 15.3 5.6 8 - 16 55 5.8 - - 16.7 58 MHz dB dB MHz ns
at 4 MHz signal frequency 52
1999 May 03
42
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA4978H
MAX.
UNIT
Analog Y, U and V output filters (3rd-order linear phase filter with notch at fCLK) f(-3dB) (0.5) sb fnotch td(g) td(g)(tol) Notes 1. With AGC at -3 dB, Y full ADC range is obtained at Vi = 1.41 V; with AGC at 6 dB, Y full ADC range is obtained at Vi = 0.5 V; with AGC at -3 dB, U full ADC range is obtained at Vi = 1.89 V; with AGC at 6 dB, U full ADC range is obtained at Vi = 0.67 V; with AGC at -3 dB, V full ADC range is obtained at Vi = 1.48 V; with AGC at 6 dB, V full ADC range is obtained at Vi = 0.52 V; at AGC attenuation more than 0 dB, where the input signal has an amplitude above the nominal value, the input processing and transfer function may have decreased specification. 2. DNL is defined as deviation of the code length from the average code length in LSB; qn DNL = max(---------------- ) : 0.99LSB means no missing code. q av - 1 3. Measurements taken using video analyzer VM700A at YUV output, control bit SEL_1FH (address 391H) set to logic 1, internal analog filters off, AGC gain (addresses 302H, 303H and 304H) set to 074H, digital processing in between, digital filters off, sampling frequency of 16 MHz. 4. Supply Voltage Ripple Rejection (SVRR) is a relative variation of the full scale analog input for a supply variation of 0.25 V over a frequency range from 20 Hz to 50 kHz. This includes 12fV, fV, 2fV, fH and 2fH which are major load frequencies. 5. Measurements carried out using Modulation Domain Analyzer HP53310A after change of control bit PLL_OPEN (address 376H) from logic 1 to logic 0 (open to closed-circuit). Control bits PLL_CK (address 375H) set to logic 0. Control bits PLL_CD (address 375H) set to 7. 6. The outputs are able to drive an external low-pass filter without slewing. In fH and 2fH this filter is of the type as described in Fig.6. For calculating an output filter the typical output impedance is also given in Fig.6. 7. The output levels for U and V have 1 dB reserve headroom in case of a 75% saturated colour bar. The maximum levels are 1.33 V + 1 dB = 1.49 V for U and 1.05 V + 1 dB = 1.18 V for V. Due to 1 dB headroom the typical AGC setting to obtain 0 dB from input to output for U and V is 83. 8. The AC characteristics are in accordance with the I2C-bus specification for fast mode (clock frequency maximum 400 kHz). Information about the I2C-bus can be found in the brochure "I2C-bus and how to use it" (order number 9398 393 40011). 3 dB down frequency attenuation at (16 MHz)
1 f 2 CLK
11.3 7 32 tuned to 12fCLK 30.6 -
11.7 8 - 32 28 -
12.1 - - 33.4 31 5
MHz dB dB MHz ns ns
stop band attenuation (after notch) notch frequency group delay group delay tolerance between channels
at 8 MHz signal frequency 26
1999 May 03
43
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SAA4978H
handbook, full pagewidth
tf 90%
tr 90% 1.5 V 10%
CLOCK 10%
INPUT DATA
MHB175
tsu(i)
th(i)
OUTPUT DATA
data valid th(o)
data transition period
td(o)
Fig.4 Data input/output timing diagram.
handbook, full pagewidth
CLK32
CLK16
MHB176
thLO tdLO
thHO tdHO
Fig.5 Timing relationship between CLK32 and CLK16.
1999 May 03
44
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SAA4978H
handbook, full pagewidth
typical output impedance internally
external load 5 H (2.5)
90 Vbuffer 0.3 0.5 H 70 200 Cp = 10 pF 20 pF (10) Vo 51 pF (25.5) 210 pF (105)
MHB177
Possible external load to be driven by output buffer without slewing. Cp is including parasitic capacitance of the application. Values in brackets are 2fH mode.
Fig.6 Output load circuit.
handbook, full pagewidth
4.43 MHz burst 0.2 V 1.0 V
64 s
MHB178
Fig.7 Test signal for differential gain and phase measurements.
1999 May 03
45
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1999 May 03
S1 S2 S3 CDCLK tW(ALE) tLLIV ALE tAVLL tLLPL tPLIV PSEN
Philips Semiconductors
Picture Improved Combined Network (PICNIC)
S4
S5
S6
tW(PSEN)
46
tLLAX A0 to A7 tAVIV PORT 0 PORT 2
tPLAZ tPXIX
tPXIZ
INSTRUCTION INPUT
A8 to A15
MHB179
Product specification
SAA4978H
Fig.8 Program memory access timing.
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
Table 1 I/O PIN YX8 YX7 YX6 YX5 YX4 YX3 YX2 YX1 YX0 UVX8 UVX7 UVX6 UVX5 UVX4 UVX3 UVX2 UVX1 UVX0 Note 1. Index X refers to different I/O buses: a) X = A: output to PALplus. b) X = B: input from PALplus, MPEG. c) X = C: output to first field memory for 2fH applications. d) X = D: input from SAA4990H, SAA4991WP. The first index digit defines the sample number, the second defines the bit number. Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 Y0L U07 U06 V07 V06 - - - - U0L YUV formats; note 1 4 : 1 : 1 FORMAT Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y1L U05 U04 V05 V04 - - - - - Y27 Y26 Y25 Y24 Y23 Y22 Y21 Y20 Y2L U03 U02 V03 V02 - - - - V0L Y37 Y36 Y35 Y34 Y33 Y32 Y31 Y30 Y3L U01 U00 V01 V00 - - - - - 4:2:2 FORMAT Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 Y0L U07 U06 U05 U04 U03 U02 U01 U00 U03 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y1L V07 V06 V05 V04 V03 V02 V01 V00 V03 U07 U06 U05 U04 U03 U02 U01 U00 U0L - - - - - - - - - 4 : 2 : 2 FORMAT DOUBLE CLOCK Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 Y0L - - - - - - - - - V07 V06 V05 V04 V03 V02 V01 V00 V0L - - - - - - - - - Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y1L - - - - - - - - -
SAA4978H
4 : 2 : 2 DPCM FORMAT Y07 Y06 Y05 Y04 Y03 Y02 Y01 Y00 Y0L UC03 UC02 UC01 UC00 - - - - - Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y1L VC03 VC02 VC01 VC00 - - - - -
1999 May 03
47
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SAA4978H
handbook, full pagewidth
CLK
WE prequalifier mode WE qualifier mode
YX8 * * * * * UX0 * * * * * * * * * *
Y7 * * * * * YL
Y7 * * * * * YL
Y7 * * * * * YL
Y7 * * * * * YL
Y7 * * * * * YL
Y7 * * * * * YL
Y7 * * * * * YL
Y7 * * * * * YL * * * * *
UVX8
U7
U5
U3
U1
U7
U5
U3
U1
UVX7
U6
U4
U2
U0
U6
U4
U2
U0
UVX6
V7
V5
V3
V1
V7
V5
V3
V1
UVX5
V6
V4
V2
V0
V6
V4
V2
V0
UVX0
UL
VL
UL
VL
MHB180
Fig.9 YUV data relationship defined by rising edge of WE in 4 : 1 : 1 format.
1999 May 03
48
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1999 May 03
SNCL write sequence: SDNA driven by SAA4978H read sequence: SDNA driven by SAA4978H a0 a1 a2 a3 a4 a5 a6 a7 a0 a1 a2 a3 a4 a5 a6 a7 SDNA driven by slave
Philips Semiconductors
Picture Improved Combined Network (PICNIC)
HIGH LOW
w0
w1
w2
w3
w4
w5
w6
w7
HIGH 3-state LOW
HIGH 3-state LOW
r0
r1
r2
r3
r4
r5
r6
r7
HIGH 3-state LOW
49
HIGH SNCL t su(o) SDNA driven by SAA4978H read sequence: SDNA driven by SAA4978H SDNA driven by slave a6 a7 t h(SNCL) a6 50% t h(o) a7 t o(dis) HIGH 3-state LOW HIGH 3-state LOW w0 w1 HIGH 3-state LOW 50% 50% LOW write sequence: r0 t su(SNCL) r1
Product specification
SAA4978H
MHB181
Fig.10 Timing diagram for SNERT bus.
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CLK32 CLK16 SNDA SNCL RSTW RSTW PALPLUS MODULE WEA 62 DIFFIN YIN 23 UIN 25 21 18 bus A 43 to 51 53 to 61 18 bus B 66 WEB 1 SNDA 2 SNCL 8 67 to 84
12 APPLICATION INFORMATION
Philips Semiconductors
RSTW 9
handbook, full pagewidth
Picture Improved Combined Network (PICNIC)
CLK32
CLK16
SNDA
SNCL
RSTR
1fH TO 2fH CONVERSATION PLUS 2fH FEATURES
RSTR
CLK32 89
CLK16 88
WEC
18 bus C
18 bus D
RED
113 114 to 122 124 to 132
110 91 to 99 101 to 109 12
YOUT
14
UOUT
15
VOUT
50
VIN 26
SAA4978H
18 HDFL
HA 28 VA 29 FBL 10 4 SCL 5 SDA 7 WDRST 6 RST 34 OSCI 12 MHz 35 OSCO 36 TEST 37 TRST 1 k CL35 38 TMS 39 TDI 40 TDO 41 TCK
19
VDFL
MHB182
CL34
Product specification
SAA4978H
Fig.11 Application diagram.
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
SAA4978H
handbook, halfpage
Rser1(xtal)
Cpar(xtal)
MHB183
Fig.12 Equivalent circuit of crystal.
handbook, full pagewidth
output
co rin
fin
co
ar
se
co
rin
e
g
g
input
MHB184
Fig.13 Peaking coring transfer curves.
1999 May 03
51
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
13 PACKAGE OUTLINE QFP160: plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height
SAA4978H
SOT322-2
c
y
X
A 120 121 81 80 ZE
e E HE A A2 A1 (A 3) Lp L detail X 41 1 bp D HD wM ZD B vM B 40 vM A
wM bp pin 1 index 160
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.07 A1 0.50 0.25 A2 3.70 3.15 A3 0.25 bp 0.38 0.22 c 0.23 0.13 D (1) 28.1 27.9 E (1) 28.1 27.9 e 0.65 HD HE L 1.6 Lp 1.03 0.73 v 0.3 w 0.15 y 0.1 Z D(1) Z E (1) 1.5 1.1 1.5 1.1 7 0o
o
31.45 31.45 30.95 30.95
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT322-2 REFERENCES IEC JEDEC MO112DD1 EIAJ EUROPEAN PROJECTION
ISSUE DATE 96-03-14 97-08-04
1999 May 03
52
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
14 SOLDERING 14.1 Introduction to soldering surface mount packages
SAA4978H
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 14.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 14.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 230 C. 14.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1999 May 03
53
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
14.5 Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, SQFP PLCC(3), SO, SOJ not suitable suitable(2) suitable not recommended(3)(4) not recommended(5) suitable suitable suitable suitable suitable HLQFP, HSQFP, HSOP, HTSSOP, SMS not LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes
SAA4978H
REFLOW(1)
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 May 03
54
Philips Semiconductors
Product specification
Picture Improved Combined Network (PICNIC)
15 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA4978H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 16 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1999 May 03
55
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 68 9211, Fax. +359 2 68 9102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381, Fax. +1 800 943 0087 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V, Tel. +45 33 29 3333, Fax. +45 33 29 3905 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615 800, Fax. +358 9 6158 0920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 4099 6161, Fax. +33 1 4099 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 2353 60, Fax. +49 40 2353 6300 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381, Fax. +1 800 943 0087 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1999
Internet: http://www.semiconductors.philips.com
SCA63
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545004/00/02/pp56
Date of release: 1999 May 03
Document order number:
9397 750 05277

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